Data held by a memory cell is more and more becoming multi-level data in semiconductor storage devices such as the NAND flash memory. Therefore, it is required to narrow the threshold distribution of each memory cell.
Also, recently, a space between adjacent memory cells becomes narrower in accordance with such minimization. As a result, when writing data, for example, due to an effect of the adjacent memory cell, a threshold varies. This causes breakage and misreading of the data.
Also, when the threshold distribution of the memory cells becomes higher than an initial one due to the variation of the threshold, it becomes necessary to raise a voltage to be transferred to a non-selected word line WL at the time of data reading. This is regarded as a factor leading to degradation of the semiconductor storage device, and causes read disturb.
Therefore, in order to minimize the effect of the adjacent memory cell, the threshold distribution of the memory cells is adjusted by various writing methods that take into account an effect of the threshold.
However, when the threshold distribution is adjusted, the design of a controller and the like needs to be changed and a circuit area of the controller becomes larger.
Also, it is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2005-25898 that the threshold adjustment between the adjacent memory cells in a bit line direction is not sufficient even when the threshold distribution of the memory cells may be adjusted between the memory cells in a word line direction.